A 100 nm CMOS technology with "sidewall-notched" 40 nm transistors and SiC-capped Cu/VLK interconnects for high performance microprocessor applications

25 June 2003

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 66-67
https://doi.org/10.1109/vlsit.2002.1015390

Abstract

A 40 nm CMOS transistor, an ultra high density 6T SRAM cell, and 10-level Cu interconnects and very-low-k (VLK) dielectrics for high performance microprocessor applications are presented. Key process features are the following: (1) High-NA 193 nm photolithography with phase shift mask and optical proximity correction (OPC) allows 40 nm gate length and the smallest 6T SRAM cell ( Author(s) Nakai, S. Fujitsu Labs. Ltd., Tokyo, Japan Takao, Y. ; Otsuka, S. ; Sugiyama, K. ; Ohta, H. ; Yamanoue, A. ; Iriyama, Y. ; Nanjyo, R. ; Sekino, S. ; Nagai, H. ; Naitoh, K. ; Nakamura, R. ; Sambonsugi, Y. ; Tagawa, Y. ; Horiguchi, N. ; Yamamoto, T. ; Kojima, M. ; Satoh, S. ; Sugatani, S. ; Sugii, T. ; Kase, M. ; Suzuki, K. ; Nakaishi, M. ; Miyajima, M. ; Ohba, T. ; Hanyu, I. ; Yanai, K.

Keywords

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