A very high speed architecture for simulated annealing

1 May 1992

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in Computer

Vol. 25 (5) , 27-36
https://doi.org/10.1109/2.144393

Abstract

A class of scheduling problems that can be modeled by using very simple cost measures, namely, counting costs and distance-measure costs, is presented. These measures can be incorporated into a simulated annealing algorithm, providing a robust system for solving such scheduling problems. A special-purpose computer architecture that supports the simulated annealing of such problems is described. This architecture provides speeds greatly surpassing those of conventional workstations and supercomputers using the same algorithm.

Keywords

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