Selective Electroless Ni‐Cu(P) Deposition for Via Hole Filling and Conductor Pattern Cladding in VLSI Multilevel Interconnection Structures

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Abstract
The selective electroless Ni‐Cu(P) deposition process has been investigated for via hole filling and conductor pattern cladding in VLSI multilevel interconnection structures. Cu was added to Al‐Si in order to deposit Ni‐Cu(P) on Al‐Si‐Cu lines without any activation step and obtain a good selectivity. It was observed that a 0.2 μm Ni‐Cu(P) overcoat on a 0.5 μm Al‐Si‐Cu line increases corrosion resistance, suppresses hillock formation, and decreases the resistance of interconnection. The Ni‐Cu(P) was deposited into via holes on Ni‐Cu(P) overcoats of Al‐Si‐Cu lines without any activation. Via holes in a 1.5 μm polyimide layer were filled by Ni‐Cu(P) to the top surface to give completely planarization of interconnections. Good contact resistance has also been obtained without any annealing by measuring the via chain resistance. For comparison, selective electroless Ni(P) deposition on Al‐Si with Pd activation was also investigated. Undesired Ni(P) deposition on a dielectric surface between Al‐Si lines was obtained after electroless Ni(P) deposition with Pd activation of Al‐Si lines. The electric potential distribution between aluminum lines on a dielectric layer was estimated using Poisson's equation to explain the poor selectivity due to surface activation of dielectric after the treatment in a Pd solution.

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