Graphical Analysis of a Digital Phase-Locked Loop
- 1 January 1979
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Aerospace and Electronic Systems
- Vol. AES-15 (1) , 88-94
- https://doi.org/10.1109/taes.1979.308799
Abstract
Under the assumption of negligible quantization error effect and no noise, a nonuniform sampling first-order digital phase-locked loop (DPLL) is analyzed by a graphical method which displays limit cycles and the cycle slipping phenomenon. The analysis suggests an upper bound to the model gain and, consequently, to the pull-in range. Moreover, this method enables one to obtain a closed-form expression of the acquisition time, accurate enough for the cases of practical interest.Keywords
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