A fetch-and-op implementation for parallel computers
- 17 May 1988
- journal article
- Published by Association for Computing Machinery (ACM) in ACM SIGARCH Computer Architecture News
- Vol. 16 (2) , 384-392
- https://doi.org/10.1145/633625.52443
Abstract
An efficient fetch-and-op circuit is described. A bit-serial circuit-switched implementation requires only 5 gates per node in a binary tree. This versatile circuit is also capable of test-and-set primitives (priority circuits) and swap operators, as well as AND and OR operations used in SIMD tests such as “branch on all carries set.” It provides an alternative implementation for the combining fetch-and-add circuit to the one designed for the Ultracomputer project; this implementation is suited to SIMD computing and can be adapted to MIMD computing.Keywords
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