A 9ns Electrically Erasable Cmos Programmable Logic Device

• 1 January 1988
• conference paper
• Published by Institute of Electrical and Electronics Engineers (IEEE)
• p. 146
• https://doi.org/10.1109/isscc.1988.663672

Abstract

Keywords

• PROGRAMMABLE LOGIC DEVICES
• TESTING
• VOLTAGE
• CMOS TECHNOLOGY
• CIRCUITS
• DELAY
• LATTICES
• PROGRAMMABLE LOGIC ARRAYS
• LOGIC DEVICES
• JOSEPHSON JUNCTIONS