Techniques for implementing two-dimensional wafer-scale processor arrays

Abstract
This paper describes some of the techniques that are being used to implement a two-dimensional wafer-scale processor array. Manufacturing defects on the wafer are tolerated by using hierarchical redundancy. This strategy employs programmable links at the highest sub-system level to ensure good electrical isolation against gross defects, while lower down in the hierarchy, transistor switches are used to reduce the overall test and programming overhead.This technique enables a logical two-dimensional array of cells to be efficiently mapped onto a larger but flawed array. A row-configuring algorithm is proposed and simulation results are given for 8 × 8 and 16 × 16 arrays by assuming a uniform distribution of defects across the wafer. An empirical yield model and a novel programmable link are also described.

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