An optimum parallel architecture for high-speed real-time digital signal processing

1 February 1988

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in Computer

Vol. 21 (2) , 47-57
https://doi.org/10.1109/2.18

Abstract

The authors describe a parallel processing architecture for real-time digital signal processing that has demonstrated virtually 100% data processing efficiency in a number of areas. The Teamed-Architecture Signal Processor (T-ASP) is a field-proven, commercially available optimal system solution to the extremely high computational and I/O rates encountered in modern digital-signal-processing environments. The design of T-ASP involves the consideration and implementation of many architectural concepts used to enhance the performance of a computer, including programmability, parallel processing, vector processing and pipelining, memory interleaving, double cache memories, multiple high-speed I/O interfaces, and segmentation of the processors for elimination of both CPU and data-handling overhead. The authors discuss hardware architecture design and implementation; hardware management; and software architecture design and implementation.

Keywords

This publication has 2 references indexed in Scilit:

Guest Editor's Introduction Interconnection Networks for Parallel and Distributed Processing
Computer, 1987
Computer architecture for digital signal processing
Proceedings of the IEEE, 1985