High-performance clock routing based on recursive geometric matching

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Abstract
Minimizing clock skew is a very,important,problem in the design of high performance,VLSI systems. We present,a general clock routing scheme that achieves extremely small clock skews, while still using a reasonable amount,of wire,length.,This routing solution is based on the construction,of a binary tree using recursive geometric,mat,thing.,We show that in the,average,case the total wire length of the,perfect,path-balanced,tree is within,a constant,factor,of the wire length in an,opt imal Steiner tree, and that in the worst case, is bounded by,O(@),when,the,n leaves are arbitrarily distributed in the unit square. we tested our algorithm,on numerous random examples and also on industrial benchmark circuits and obtained very promising results:,our,clock routing,yieIds,near-zero average clock skew while using similar or even shorter total wire length in comparison with the methods of [7].

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