Error-Control Techniques for Logic Processors
- 1 December 1972
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-21 (12) , 1331-1336
- https://doi.org/10.1109/T-C.1972.223504
Abstract
A new error-control technique for logic processors is given. The proposed technique uses Reed-Muller codes (RMC's). The design scheme given has better efficiency than the schemes proposed earlier. The improved efficiency is obtained by relaxing a basic assumption originally made by Elias. Furthermore, it is shown that the efficiency of the proposed scheme asymptotically approaches the maximum efficiency achievable by a practical though restricted class of error-control schemes. Reliability of the proposed scheme is studied.Keywords
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