An NMOS digital signal processor with multiprocessing capability

1 January 1985

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXVIII, 90-91
https://doi.org/10.1109/isscc.1985.1156830

Abstract

This paper will describe a second generation 8-13MIP multi-tasking DSP with a 544×16b RAM and single cycle multiply/accumulation instructions. The chip is implemented with 2.4μ NMOS technology.

Keywords

MOS DEVICES
DIGITAL SIGNAL PROCESSORS
RANDOM ACCESS MEMORY
READ-WRITE MEMORY
DIGITAL SIGNAL PROCESSING
REGISTERS
COMPUTER ARCHITECTURE
CONCURRENT COMPUTING
HARDWARE
ARITHMETIC

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