Fault-tolerance in a high-speed 2D convolver/correlator: Starloc
- 7 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Starloc (Sandia target location computer), a special-purpose computer for locating 3D objects in a 2D image using a generalized correlation filter algorithm, is described. Starloc performs high-speed 2D convolution/correlation using commercially available floating-point processors and was designed with fault tolerance as a central feature. Its basic architecture consists of ten pipeline stages (eight for fast Fourier transform (FFT) processing and two for pixel-by-pixel weighting), arranged in a ringlike structure that includes two hot-standby stages for replacing any failed stage. Protection techniques from bit-level parity up through algorithm-based methods are used. All data paths involving memory through and within the distributed sections are covered by standard binary error-correcting codes. The floating-point processors are duplicated and surrounded by appropriate comparison circuits to detect failures while the overall system function is protected by algorithm-based checks. Dual bit-slice sequencers use internal comparators and the regular memory addressing in both FFT and weighting sections uses fault-tolerant counters. Design and fabrication of a prototype have been completed.Keywords
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