Size optimization for CMOS basic cells of VLSI
- 1 January 1991
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 2180-2183 vol.4
- https://doi.org/10.1109/iscas.1991.176722
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- ECSTASY: a new environment for IC design optimizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- TILOS: A Posynomial Programming Approach to Transistor SizingPublished by Springer Nature ,2003
- DELIGHT.SPICE: an optimization-based system for the design of integrated circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Transistor sizing in CMOS circuitsPublished by Association for Computing Machinery (ACM) ,1987
- Aesop: a tool for automated transistor sizingPublished by Association for Computing Machinery (ACM) ,1987
- An algorithm for CMOS timing and area optimizationIEEE Journal of Solid-State Circuits, 1984
- An interactive linear programming approach to model parameter fitting and worst case circuit designIEEE Transactions on Circuits and Systems, 1980