A layout checking system for large scale integrated circuits

1 June 1988

proceedings article
Published by Association for Computing Machinery (ACM)

p. 163-171
https://doi.org/10.1145/62882.62899

Abstract

This paper describes a new design rule checking system for LSI mask patterns. Major features of the system are a relatively small computing time needed, even for very large circuits (e.g. 10,000 elements), wide applications to a variety of fabrication processes, due to its functional flexibility, and minimized spurious errors.

Keywords

FABRICATION PROCESS
LSI MASK PATTERN
SMALL COMPUTING TIME
FUNCTIONAL FLEXIBILITY
NEW DESIGN RULE CHECKING
WIDE APPLICATION
LAYOUT CHECKING SYSTEM
SPURIOUS ERROR
LARGE CIRCUIT
LARGE SCALE
INTEGRATED CIRCUIT
MAJOR FEATURE
DESIGN RULE CHECKING

This publication has 1 reference indexed in Scilit:

Design rule checking and analysis of IC mask designs
Published by Association for Computing Machinery (ACM) ,1976