A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19 Gb/s decision circuit using 0.2 μm GaAs MESFET
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 193-196
- https://doi.org/10.1109/gaas.1994.636965
Abstract
This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs SCFL Logic. We reveal the high-speed operation mechanism of HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series gated master slave flip-flops and HLO-FFs based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision ICs confirm the accuracy of our analytical method and the high speed operation of a HLO-FF decision circuit at 19 Gb/s.Keywords
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