A sub-40 ps ECL circuit at a switching current of 1.28 MA

1 January 1987

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 371-374
https://doi.org/10.1109/iedm.1987.191434

Abstract

A sophisticated bipolar technology for high speed and low power dissipation VLSI's has been developed. It employs an Emitter-base Self-aligned structure with Polysilicon Electrodes and Resistors (ESPER) combined with U-FOX (U-groove isolation with thick Field OXide). An ECL circuit with a minimum gate delay time of 38.8 ps has been obtained at a switching current (ICS) of 1.28 mA. At the same time, we have fabricated low power type transistors. In this circuit, we have obtained a minimum gate delay time of 60.2 ps at ICSof 0.34 mA and a wiring length effect of 50 ps/mm for a 0.32 mA emitter follower current. This new process is advantageous to high performance VISI's and giga-digital systems.

Keywords

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