An Investigation Of The Performance Of Various Dynamic Scheduling Techniques

This publication has 9 references indexed in Scilit:

• Hiding Memory Latency using Dynamic Scheduling in Shared-Memory Multiprocessors
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• Limits of instruction-level parallelism
  Published by Association for Computing Machinery (ACM) ,1991
• The effect of context switches on cache performance
  Published by Association for Computing Machinery (ACM) ,1991
• Two-level adaptive training branch prediction
  Published by Association for Computing Machinery (ACM) ,1991
• Checkpoint Repair for High-Performance Out-of-Order Execution Machines
  IEEE Transactions on Computers, 1987
• HPSm, a high performance restricted data flow architecture having minimal functionality
  ACM SIGARCH Computer Architecture News, 1986
• HPS, a new microarchitecture: rationale and introduction
  Published by Association for Computing Machinery (ACM) ,1985
• Critical issues regarding HPS, a high performance microarchitecture
  Published by Association for Computing Machinery (ACM) ,1985
• An Efficient Algorithm for Exploiting Multiple Arithmetic Units
  IBM Journal of Research and Development, 1967