PART: Programmable Array Testing Based on a Partitioning Algorithm
- 1 April 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 3 (2) , 142-149
- https://doi.org/10.1109/tcad.1984.1270068
Abstract
PART is a system for PLA testing and design verification, intended to be properly interfaced with other existing tools to generate a comprehensive design environment. To this purpose, it provides several facilities, among which the capability of generating a fault population on the basis of layout information. PART aims at producing a very compact test set for all detectable crosspoint defects, using limited amounts of run time and storage. This is achieved by means of an efficient partitioning algorithm together with powerful heuristics. Test minimality is ensured by a simple procedure. In the present paper these are discussed, experimental results are given and a comparison with competing strategies is madeKeywords
This publication has 9 references indexed in Scilit:
- Verification TestingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- Techniques for programmable logic array foldingPublished by Association for Computing Machinery (ACM) ,1982
- Design aids for VLSI: The Berkeley perspectiveIEEE Transactions on Circuits and Systems, 1981
- Design Automation and the Programmable Logic Array MacroIBM Journal of Research and Development, 1980
- A Heuristic Test-Pattern Generator for Programmable Logic ArraysIBM Journal of Research and Development, 1980
- Detection of Faults in Programmable Logic ArraysIEEE Transactions on Computers, 1979
- Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's)IEEE Transactions on Computers, 1979
- An Introduction to Array LogicIBM Journal of Research and Development, 1975
- Recursive Operators for Prime Implicant and Irredundant Normal Form DeterminationIEEE Transactions on Computers, 1970