Parallel error correction algorithm in RNS VLSI digital circuits
- 1 January 1988
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
An important problem in real-time DSP (digital signal-processing) systems with highly integrated components is the capability of automatic error detection and correction. The use of residue number arithmetic allows error detection and correction because of its unweighted nature. A single-error-correction procedure is proposed which is based on the use of redundant residue number systems (RRNS) and the base extension operation. The proposed method uses a small decision table and works in parallel mode; therefore it is suitable for high-speed VLSI circuit realization. A parallel architecture which realizes the method is also introduceKeywords
This publication has 3 references indexed in Scilit:
- Error Correction in Redundant Residue Number SystemsIEEE Transactions on Computers, 1973
- Error Correction in Residue ArithmeticIEEE Transactions on Computers, 1972
- Self-checked computation using residue arithmeticProceedings of the IEEE, 1966