Hardware logic simulation by compilation
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 712-715
- https://doi.org/10.1109/dac.1988.14848
Abstract
A behavioral and logic simulation system which uses extensive optimization and compilation techniques to obtain high performance is described. It incorporates data-flow analysis to optimize the evaluation of unordered assignment statements that define a hardware structure, and to extract clocking rules. An integral code generator produces efficient assembly code for three different machines, and an associated run-time library provides a flexible interactive debugging environment.Keywords
This publication has 2 references indexed in Scilit:
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