Module Clustering to Minimize Delay in Digital Networks
- 1 January 1969
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-18 (1) , 47-57
- https://doi.org/10.1109/t-c.1969.222524
Abstract
An important aspect of the packaging of digital networks is the allocation of logic gates to modules such that a predetermined objective function is minimized. In order to develop techniques for this partitioning of a logic network we have considered the following problem: Given an acyclic combinational network composed of various primitive blocks such as NOR gates, assume that a maximum of M gates can be "clustered" together into larger modules, and that a maximum of P pins can be accommodated in each larger module. Assume also that in a network composed of such larger modules, no delay is encountered on the interconnections linking two gates internal to a module and a delay of one time unit is encountered on interconnections linking two gates in different modules . Find an easily applied algorithm that will result in a network such that the maximum delay through the network is minimized.Keywords
This publication has 2 references indexed in Scilit:
- General survey of design automation of digital computersProceedings of the IEEE, 1966
- Electrical Assemblies with a Minimum Number of InterconnectionsIEEE Transactions on Electronic Computers, 1962