Bipolar CMOS merged structure for high speed M bit DRAM

• 1 January 1986
• conference paper
• Published by Institute of Electrical and Electronics Engineers (IEEE)
• p. 802-804
• https://doi.org/10.1109/iedm.1986.191317

Abstract

Keywords

• RANDOM ACCESS MEMORY
• BIPOLAR TRANSISTORS
• CMOS TECHNOLOGY
• MOSFET CIRCUITS
• ERROR ANALYSIS
• FABRICATION
• DRIVER CIRCUITS
• LABORATORIES
• CAPACITANCE
• CMOS PROCESS