Low-resistance MOS technology using self-aligned refractory silicidation
- 1 September 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 31 (9) , 1329-1334
- https://doi.org/10.1109/t-ed.1984.21708
Abstract
A new low-resistance MOS technology has been developed for use in VLSI's with scaled MOSFET's. A new MOSFET is featured by gate and source-drain being refractory silicided in self-alignment and isolated from one another, even without any insulating spacers on gate sides. An essential part of the MOSFET fabrication process is the ion implantation through metal (ITM) silicidation technique, which consists of ion-beam-induced metal-silicon interface mixing and appropriate annealings to form high-quality refractory metal silicides in self-alignment with silicon patterns and with good reproducibility.Keywords
This publication has 0 references indexed in Scilit: