An architecture for a speech recognition system
- 1 January 1983
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. XXVI, 118-119
- https://doi.org/10.1109/isscc.1983.1156528
Abstract
A realtime system using parallel processing and pipeline techniques to implement the pattern alignment operation will be reported. A 3.5mm × 4.2mm chip has been fabricated in 5μ NMOS technology.Keywords
This publication has 2 references indexed in Scilit:
- A monolithic audio spectrum analyzer for speech recognition systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- A microcomputer with digital signal processing capabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982