Enhanced mobility top-gate amorphous silicon thin-film transistor with selectively deposited source/drain contacts
- 1 February 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 13 (2) , 80-82
- https://doi.org/10.1109/55.144965
Abstract
Amorphous silicon thin-film transistors (TFTs), in a top-gate staggered electrode structure have been prepared using selectively deposited doped silicon contact layers, formed in-situ by plasma-enhanced chemical vapor deposition (PECVD). Selective deposition reduces the number of processing steps and assures the formation of low-resistance contacts. Devices fabricated with two photomasks and one plasma deposition step show saturation and linear mobilities as high as 1.1 and 0.9 cm/sup 2//V-s, respectively, with threshold voltages between 3 and 6 V. On/off ratios are >10/sup 6/, with a subthreshold slope of 0.8 V/decade. The mobilities are at least a factor or 2 higher than previously reported for top-gate structures and are similar to values reported for bottom-gate (inverted staggered) TFTs.Keywords
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