Advanced Hi-CMOS device technology

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Abstract
A second generation high performance CMOS (Hi-CMOSII) device technology has been developed using a 2µm process. In the Hi-CMOSII technology, fine patterns were formed using dry etching processes and a high resolution aligner. Short channel MOS transistors having 2 µm typical gate length are formed in separate low carrier concentration p and n wells. To improve the threshold voltage controllability, a thin gate oxide and shallow junction are employed in the Hi-CMOSII. To increase the breakdown voltage of n channel devices, graded junctions are formed. The latch up effect was also eliminated. This Hi-CMOSII device technology achieved a 1fJ CMOS logic. It was also applied to high speed, low power static RAMs employing newly developed memory cells.

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