DIRECS: system design of a 100 Mbit/s digital receiver

1 January 1992

journal article
Published by Institution of Engineering and Technology (IET) in IEE Proceedings G Circuits, Devices and Systems

Vol. 139 (2) , 222-230
https://doi.org/10.1049/ip-g-2.1992.0037

Abstract

The advances in VLSI technology have made the digital implementation of data receivers feasible at very high data rates. Aspects of the design of a chip set representing a 100 Mbit/s digital receiver for coded 8-PSK modulation are described. The receiver is discussed as an example of complex system design and finally implementation aspects are presented. Special emphasis is given to design methodology, trade-off optimisation and performance results. Attention is paid to the importance of considering the structural and algorithmic design as an integral part of the implementation process to obtain an efficient solution.

Keywords

PERFORMANCE
SYSTEM DESIGN
DIGITAL IMPLEMENTATION
CHIP SET DESIGN
HIGH DATA RATES
IMPLEMENTATION ASPECTS
IMPLEMENTATION PROCESS
100 MBIT/S
CODED 8-PSK MODULATION
DESIGN METHODOLOGY
VLSI
CMOS
TRADE-OFF OPTIMISATION
ALGORITHMIC DESIGN
DIGITAL RECEIVER CHIP SET
100 MBIT/S DIGITAL RECEIVER
DIRECS
COMPLEX SYSTEM DESIGN
DATA RECEIVERS

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