Parallel turbo coding interleavers: avoiding collisions in accesses to storage elements
- 28 February 2002
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 38 (5) , 232-234
- https://doi.org/10.1049/el:20020148
Abstract
High-speed, low latency convolutional turbo codes require a parallel decoder architecture. To maximise the gain in speed, the interleaver also should have a parallel structure. Here, a class of optimum parallel interleavers regarding the access to storage elements is presented. They combine regularity (easy implementation) with no latency in data transfer between the decoder module and intrinsic/extrinsic values memories, and show excellent BER performance.This publication has 3 references indexed in Scilit:
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- Performance analysis of turbo codesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Memory optimization of MAP turbo decoder algorithmsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2001