One of the highest leverage activities for improving the profitability of manufacturing integrated circuits is probe yield improvement. The cost of manufacturing wafers is the same for low yielding wafers as for high yielding wafers. Increasing the number of good ICs per wafer therefore increases revenue markedly, and most of the increased revenue (except package and final test costs) drops to the bottom line as profit. This paper describes the financial impact of three types of yield improvement activity: (1) overall reduction of the defect density of the manufacturing line; (2) improving the yield of products which fall significantly below the "ideal" yield for a given technology; (3) increasing the rate of yield learning for products designed to new technologies. Calculations of the financial impact of these activities are presented. The paper also describes a powerful method, called Integrated Yield Analysis, for identifying and quantifying all sources of wafer probe yield loss for integrated circuits. Since many IC manufacturers adequately classify and quantify yield loss relating to random defects, this paper emphasizes the accurate calculation of yield limits resulting from systematic causes.