Optimization of nonplanar power MOS transistors

1 October 1978

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 25 (10) , 1229-1234
https://doi.org/10.1109/T-ED.1978.19257

Abstract

Analysis of fundamental MOSFET parameters predicts device limits in high-voltage high-speed operation that exceed the performance of bipolar devices. The optimization of voltage, speed, and "on" resistance parameters for power MOSFET's suggests a vertical three-terminal device design with short, wide channels; a wide, lightly doped drain region; and field terminator rings at the device perimeter. Utilizing this design philosophy, VMOS transistors have been produced with source-drain breakdown voltage greater than 450 V, and 5.5-Ω "on" resistance for 2.0-mm2active area. With a high channel width packing density design and 2.5-mm2active area, a 30-V transistor has also been produced having only 0.060-Ω "on" resistance. The breakdown voltage and "on" resistance of these devices exceed the performance of other power MOSFET's currently available. Also, the switching speed of these devices (better than 15 ns) far exceeds the performance of high-voltage bipolar transistors. Measurements of drain leakage current at 200-V drain potential show a resistance ratioR_{off}/R_{on}of approximately 1010for a 20-V variation in gate-to-source voltage.

Keywords

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