Harmonic analysis and improvement of a new solid-state fault current limiter
- 1 January 2001
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. D5/1-D5/8
- https://doi.org/10.1109/repcon.2001.949528
Abstract
This paper presents a harmonic study on a newly developed solid-state fault current limiter. Using this device, the supply voltage sag is reduced when a short-circuit fault occurs on a cable feeder in the downstream network, hence improving the power quality. The device will eventually isolate the faulted part from the healthy network. Harmonics caused by the fault current limiter are analysed and a method is proposed to prevent undesirable harmonic interactions. Analytical and experimental results are compared with existing regulations. It is verified that, with precautions, the operation of the solid-state fault current limiter will not cause problems to either the supply network or the loads.Keywords
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