Reduction of Charge Build-Up during Reactive Ion Etching by Using Silicon-On-Insulator Structures
- 1 March 1997
- journal article
- Published by IOP Publishing in Japanese Journal of Applied Physics
- Vol. 36 (3S) , 1505-1508
- https://doi.org/10.1143/jjap.36.1505
Abstract
The charge build-up of silicon-on-insulator (SOI) structures during reactive ion etching has been investigated. The charge build-up was evaluated by using metal/nitride/oxide/silicon (MNOS) capacitors fabricated on SOI. It has been found that the charge build-up can be drastically reduced by using SOI, while the reduction in etching rate is only 3% less than that attained using bulk Si wafers at a relatively high RF power condition. The amount of charge build-up has been found to decrease the thickness of the buried oxide layer increases. A model to explain these phenomena is discussed.Keywords
This publication has 1 reference indexed in Scilit:
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