Chip Substrate Resistance Modeling Technique for Integrated Circuit Design
- 1 April 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 3 (2) , 126-134
- https://doi.org/10.1109/tcad.1984.1270066
Abstract
No abstract availableThis publication has 2 references indexed in Scilit:
- Algorithms for ASTAP--A network-analysis programIEEE Transactions on Circuit Theory, 1973
- Measurement of Sheet Resistivities with the Four-Point ProbeBell System Technical Journal, 1958