A manufacturable complementary GaAs process
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 127-130
- https://doi.org/10.1109/gaas.1993.394486
Abstract
A self-aligned complementary GaAs heterostructure FET process has been established for low power, high-speed digital circuits. The devices are fabricated on four-inch MBE epitaxial wafers consisting of AlGaAs/InGaAs epilayers grown on LEC GaAs substrates. The process uses twelve lithographic steps including two levels of interconnect metal. Typical transconductances of 250 mS/mm and 60 mS/mm are achieved on 1/spl times/10 /spl mu/m N-channel and P-channel devices, respectively. Twenty-three stage unloaded complementary ring oscillators consisting of 1/spl times/10 /spl mu/m N- and P-FETs show propagation delay of 190 ps and speed-power product of 7.5 fJ or 0.35 /spl mu/W/MHz.<>Keywords
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