On sign bit assignment for a vector multiplier
- 1 March 1976
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE
- Vol. 64 (3) , 372-373
- https://doi.org/10.1109/PROC.1976.10125
Abstract
A simple sign bit assignment scheme for each SHIFT operation of a vector multiplier is presented. This new scheme is capable of determining the correct sign for a shifted sum independent of overflow conditions during each ADD operation.Keywords
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