A GaAs 1K static RAM using tungsten silicide gate self-aligned technology
- 1 October 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 18 (5) , 520-524
- https://doi.org/10.1109/jssc.1983.1051987
Abstract
This paper reports a GaAs 1K static RAM, fabricated using tungsten silicide gate self-aligned technology with full ion implantation. With 2-/spl mu/m gate length, an address access time of 3.6 ns and a minimum write-enable pulse width of 1.6 ns were achieved with a power dissipation of 68 mW. The access time compares favorably to those of currently reported high-speed Si bipolar memories, and the greatly decreased power dissipation is better by one order of magnitude. An address access time of 0.88 ns can be achieved by shortening the gate length to 1 /spl mu/m and adopting a 2-/spl mu/m design rule in the layout.Keywords
This publication has 1 reference indexed in Scilit:
- Ti/W silicide gate technology for self-aligned GaAs MESFET VLSISPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981