Integrating Novel Packaging Technologies for Large Scale Computer Systems

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Abstract
Proximity Communication (PxC) enables VLSI chips placed face-to-face to communicate using close-field capacitive coupling. In a 90 nm standard CMOS technology, using the packaging techniques described in this paper, PxC provides chip-to-chip latency of 2.5 ns at 4 Gb/s per channel with less than 2.5 mW/Gb/s, an areal bandwidth density of 0.83 Tb/s/mm2, and a BER less than 10−15. At a system level, the benefits of PxC scale directly with the number of chips that can be packaged together, because PxC enables designers to aggregate multiple chips that perform as a single large piece of silicon. The chips can also be heterogeneous to provide an optimized mix of process technology and functionality, such as integrating DRAM chips, NAND flash memory, and CMOS processor chips. In this paper we describe packaging advances and technology prototypes that enable PxC and provide its system-level benefits.

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