Parallel processing for Viterbi algorithm

18 August 1988

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 24 (17) , 1098-1099
https://doi.org/10.1049/el:19880745

Abstract

Dual-dimensional parallelisation for the Viterbi algorithm is exploited. That is, parallelisation of the decoding procedures within each stage of the trellis and parallelisation of the decoding procedures are expanded to consecutive stages without excessive path memories. Since an arbitrary number of stages can be parallelised, the trade-off between computation speed and degree of integration can be adjusted as required.

Keywords

EXPANDED TO CONSECUTIVE STAGES
TRADE-OFF
ARBITRARY NUMBER OF STAGES
VLSI SYSTOLIC ARRAYS
VITERBI DECODING
DEGREE OF INTEGRATION
COMPUTATION SPEED
DECODING PROCEDURES
2D PARALLEL PROCESSING
VITERBI ALGORITHM
TRELLIS SEARCH PARALLELISM

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