Some Remarks on State Reduction of Asynchronous Circuits by the Paull-Unger Method

Abstract
A method is developed for the design of arbitrary length counters using three-input majority elements. The iterative nature of the design leads to circuits of extreme simplicity and regularity. The system is dc triggered, hence operating correctly regardless of the rise time or width of the clock signal. As the method does not utilize master-slave techniques, only a single-phase clock is required. A practical embodiment of the system is presented, giving correct operation at clock rates in excess of 50 Mc/s. With more sophisticated high-speed circuitry, correct operation at clock rates in excess of 100 Mc/s should be readily attainable.

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