PREP benchmarks for programmable logic devices

30 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 7.7.1-7.7.6
https://doi.org/10.1109/cicc.1993.590581

Abstract

The authors describe a set of benchmark circuits and implementation methodology for measuring logic capacity and speed performance in programmable logic devices (PLDs). PLDs include complex PLDs and field programmable gate arrays (FPGAs). The PREP (Programmable Electronic Performance Corporation) benchmarks were developed for users of PLDs to evaluate different architectures and devices for logic capacity and speed performance using common logic functions and a standard methodology.

Keywords

PROGRAMMABLE LOGIC DEVICES
LOGIC DEVICES
PROGRAMMABLE LOGIC ARRAYS
VELOCITY MEASUREMENT
FIELD PROGRAMMABLE GATE ARRAYS
INTEGRATED CIRCUIT MEASUREMENTS
CLOCKS
ROUTING
LOGIC DESIGN
LOGIC CIRCUITS

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