Capacitive coupling of floating body well to sensitive nodes prevents high-resistance CMOS circuit from latching-up

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Abstract
A new concept is derived whereby voltage transients occurring in the bulk substrate of a floating p− -well CMOS circuit can be conveniently decoupled near the sensitive n+/p− source-well parasitic junctions of n-channel transistors, thereby preventing latch-up occurrence. The ability of the well body to accommodate a nonequipotential situation is then taken advantage of to design a new and compact filter circuit that would certainly trigger latch-up if implemented on a grounded p−-well.

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