Charged defect states at silicon grain boundaries

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Abstract
Grain boundaries (GB’s) can induce electrostatic potential barriers due to trapping of majority carriers into defect states at the interface. The as-grown electrical activity of GB’s in silicon is related with the density of decorated dislocations in the interface plane. Heat treatments actuate as-grown electrically active and inactive boundaries. The measured transverse conductance is reduced due to the presence of a potential barrier. The density of these generated states is determined by duration and temperature of the treatment. We explain this actuation by impurity-related formation of trap states at the interface. The annealing-temperature dependence of the density of trap states is independent of the atomistic structure of the interface. We observe strong impurity gettering of GB’s. Hydrogen incorporation in plasma discharge can repassivate as-grown electrically active and the heat-actuated GB’s. The majority-carrier transport properties of silicon GB’s are thus determined by impurities instead of the atomistic interface structure.