40 nm gate length ultra-thin SOI n-MOSFETs with a backside conducting layer

This publication has 3 references indexed in Scilit:

• A 7.9/5.5 psec room/low temperature SOI CMOS
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Scaling the Si MOSFET: from bulk to SOI to bulk
  IEEE Transactions on Electron Devices, 1992
• Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate
  Solid-State Electronics, 1984