A 512 kb/5 ns BiCMOS RAM with 1 kG/150 ps logic gate array

Abstract
An ECL (emitter-coupled-logic) 512-kb BiCMOS SRAM (statistic random access memory) with 1-kG logic and using 0.8- mu m high-performance bipolar CMOS (Hi-BiCMOS) technology is described. The RAM has 5-ns address access time and 2-ns write-pulse width. The logic gate has 150-ps propagation delay with 4-mW power dissipation. A RAM-with-logic configuration is adopted to eliminate interconnection delay between the RAM and peripheral logic and to facilitate a wide-bit RAM. The design rule dependence of the delay time of a three-input ECL OR/NOR gate and a two-input BiCMOS NAND gate is shown. On-chip address access times, under 5 ns from address latches to data-out latches at room temperature with a marching test pattern, are also shown. Major characteristics of the LSI are presented.

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