Parallel logic simulation on general purpose machines
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 166-171
- https://doi.org/10.1109/dac.1988.14753
Abstract
Three parallel algorithms for logic simulation have been developed and implemented on a general purpose shared-memory parallel machine. The first algorithm is a synchronous version of a traditional event-driven algorithm which achieves speed-ups of 6 to 9 with 15 processors. The second algorithm is a synchronous unit-delay compiled mode algorithm which achieves speed-ups of 10 to 13 with 15 processors. The third algorithm is totally asynchronous with no synchronization locks or barriers between processors and the problems of massive state storage and deadlock that are traditionally associated with asynchronous simulation have been eliminated. The processors work independently at their own speed on different elements and at different times. When simulating circuits with little or no feedback, the asynchronous simulation technique varies between 1 to 3 times faster than the conventional event-driven algorithm using 1 processor and depending on the circuit, achieves 10 to 20% better utilization using 15 processors.Keywords
This publication has 6 references indexed in Scilit:
- Statistics for parallelism and abstraction level in digital simulationPublished by Association for Computing Machinery (ACM) ,1987
- Faster architectural simulation through parallelismPublished by Association for Computing Machinery (ACM) ,1987
- Statistics on logic simulationPublished by Association for Computing Machinery (ACM) ,1986
- Virtual timeACM Transactions on Programming Languages and Systems, 1985
- A Survey of Hardware Accelerators Used in Computer-Aided DesignIEEE Design & Test of Computers, 1984
- Asynchronous distributed simulation via a sequence of parallel computationsCommunications of the ACM, 1981