Double level interconnection system for submicron CMOS applications

Abstract
A double-level interconnection system for severe topography and fine-line submicron lithography has been developed. This system is suitable for single and double poly logic or memory interconnection. It has been successfully applied in Siemens 4-M DRAM with double poly topography. The first interconnection level is realized by a polycide layer with a minimum pitch of 1.7 mu m. The bitline contacts are self-aligned to gate and field oxide. The first level is planarized by a flowglass process using a highly doped borophosphosilicate glass. In the second interconnection level, a Ti/TiN/AlSi barrier metallisation with minimum pitch of 1.8 mu m is used. A contact-filling process using nonselective CVD-W and etchback technique has also been developed for incorporation into this metallization system.

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