Four quadrant multiplier core with lateral bipolar transistor in CMOS technology

17 January 1985

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 21 (2) , 72-74
https://doi.org/10.1049/el:19850050

Abstract

A four quadrant multiplier core using lateral bipolar transistor in CMOS technology has been fabricated, tested and analysed. It has a high precision of linearity (with an error smaller than 2% for inputs over half of the power supply voltages), small offset of a few millivolts at the inputs, a small output offset of about 1.5 mV and a small dissipation.

Keywords

FOUR QUADRANT MULTIPLIER CORE
VLSI
HIGH LINEARITY PRECISION
OUTPUT OFFSET
SMALL OFFSET
LATERAL BIPOLAR TRANSISTOR
CMOS TECHNOLOGY
DISSIPATION

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