A Design Procedure for Fault-Locatable Switching Circuits
- 1 December 1972
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-21 (12) , 1421-1426
- https://doi.org/10.1109/t-c.1972.223517
Abstract
A technique to design fault-locatable combinational switching circuits is given. The networks resulting from the application of the proposed technique have at most three levels of gates.Keywords
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