Improvement of the active load‐pull technique for the optimization of high power communication SSPAs

Abstract
This article presents recent developments in the active load‐pull technique which improve the accuracy, reliability, and efficiency of power transistor characterization. In the load‐pull system described in this article, both the active loop technique and the mismatching technique are implemented. This allows fine and accurate synthesis of load impedances anywhere on the Smith chart. The two main attractive capabilities of the proposed system are: (1) Fine and accurate characterization of highly mismatched components is made easier. This is illustrated in this article with measurement results of a 4‐W silicon bipolar transistor. (2) Load impedance areas where transistors provide their best amplification performances can be finely scanned. Therefore, data processing routines are easier, more accurate, and more efficient. This is particularly useful for the optimization of trade‐offs between power‐added efficiency and third order intermodulation in power transistor. This is demonstrated with measurement results using a 4‐W GaAs power FET.

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