Parallel implementation of binary comparison circuits
- 1 August 1979
- journal article
- research article
- Published by Taylor & Francis in International Journal of Electronics
- Vol. 47 (2) , 187-192
- https://doi.org/10.1080/00207217908938631
Abstract
A technique is proposed for implementing parallel tree-like comparator circuits with fan-in constrained gates, exhibiting logarithmic comparison time growth. The technique is based on formulating the binary comparator logic to resemble the carry look ahead logic of the binary adder. The implementation is extended to modular tree comparator networks.Keywords
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